This invention is in the field of microcomputers and microprocessors. More specifically, it is in the area of interfacing peripheral devices and/or other processors to the microcomputer or microprocessor.
A rapidly accelerating trend in the electronics industry is the increased demand for fast computational abilities. To try to meet this demand, the industry has introduced families of digital signal processing microcomputers, high-speed conventional microprocessors, and other fast processors. It is becoming apparent that one of the major bottlenecks in pushing for still higher speed is getting data in and out of the processor itself.
The industry has tried numerous approaches to solve this problem when memory access is the issue. Techniques such as pipelining, cacheing, etc. have been successfully employed. However one area that has not been adequately addressed is that of I/O to remote (i.e. off-chip) devices.
It is an object of the present invention to avoid creating an I/O bottleneck.
The vast majority of systems have a hardwired type of handshake between the microprocessor/microcomputer and the peripheral device. This handshake generally requires the processor to wait until the other device is ready during a read or a write operation. This in turn usually means that the reads and/or writes must be synchronous with the system clock.
It is an object of the present invention to allow a handshaking protocol, without forcing the processor to wait for the other device.
It is also an object of the invention to allow asynchronous reads and writes.
Asynchronous interfaces that have been developed have required several control lines to operate. This requires that the integrated circuit have more pins (increasing costs). This also adds complexity to the interface.
It is an object of the invention to minimize the number of control lines required for reads and writes.
It is also an object of the invention to simplify the interface mechanism.
Current I/O interfaces are designed to operated with fixed bus widths. If a processor has a 16 bit data bus, then peripherals are expected to be 16 bits in data width. This limits the number of devices that can be attached. In addition, if a 16 bit processor wishes to communicate with an 8 bit processor, added external logic is required.
It is an object of the invention to allow the processor to communicate with peripheral devices having varying data bus widths.
It is also an object of the invention to allow different processors having different data bus widths to communicate in a simple manner.
It is a further object of the invention to allow interface communications to occur with minimal external logic.
Asynchronous communications introduce certain problems. The receiving processor must usually poll its inputs to see when valid data is present. This slows the processor down as it must continually ask. In processors that do not have to poll the receive buffer, an interrupt is normally provided that must be triggered by the sending processor. However this takes an additional external pin, plus additional system design to implement.
It is an object of the invention to provide a mechanism for alerting a receiving processor when it has received data.
It is a further object of the invention to provide this mechanism without having to add an external interrupt pin.
It is also an object of the invention to minimize system design overhead by eliminating the requirement that the transmitting processor explicitly generates interrupts to the receiving processor.
A similar situation occurs on the transmitting side. When the processor wishes to transfer data, it needs to know when the receiving device is available. Further, the transmitting processor should be able to tell when the receiving device has read the last data transmitted.
It is an object of the invention to inform the transmitting processor when it is free to transmit data.
It is also an object of the invention to allow the transmitting processor to know when the prior transmitted data has been read.
In some cases, it is desirable for the processor to operate in a master mode. This means that all communications occur in response to the processor's initiation. Conversely, there are situations where the processor should act as a slave to another system master
It is an object of the invention to allow the interface to be able to function in either a master or a slave environment.
These and other objects of the invention are achieved by a communications system comprising:
a peripheral device in communications over a data bus with a processor;
said data bus also including a receive control line and a transmit control line, each said line having a first and second state;
said processor having reception and transmission registers selectively coupled to said data bus for the reception and transmission of data;
said peripheral device controlling said receive control line wherein said data is latched into said reception register when said receive control line state is changed from said first state to said second state, and wherein said processor is selectively interrupted when said receive control line state is changed said first state to said second state;
said peripheral device controlling said transmit control line wherein said data is placed onto said data bus from said transmission register when said transmit control line moves from said first state to said second state; and
said processor selectively changing the data in said transmission register after said transmit control line moves from said second state to said first state.